With development of processor technologies, multi-core/many-core has become a development direction of a processor structure. A multi-core/many-core processor includes multiple cores, each core can execute its own code, and cores can work cooperatively.
When multiple cores in a multi-core/many-core processor work cooperatively, different cores need to communicate with each other to implement data sharing and synchronization. As more cores are integrated on a single processor chip, complexity of communication between the cores increases. A conventional bus architecture applies only to a case with a few cores and is difficult to meet an increasingly complex communication requirement. Therefore, as a current efficient solution to communication between cores of a multi-core/many-core processor, a network-on-chip (NoC) is widely applied and becomes a mainstream interconnection technology.
Referring to a communication manner of a distributed calculation system, a network-on-chip replaces a conventional bus with routing and packet switched technologies. In a multi-core/many-core processor chip, the network-on-chip is mainly used to transmit a flit between cores and functional components, and all flit processing is completed by the cores. Separation of data transmission from data processing brings a multi-core/many-core processor more highly efficient communication between cores and good expansibility.
However, with an increasing quantity of processor cores and a constantly increasing scale of parallel tasks inside a processor chip, a larger quantity of flits need to be transmitted over the network-on-chip. In flit transmission in the prior art, when a quantity of cores reaches a specific order of magnitude, for example, dozens or more, a large quantity of flits need to be transmitted over the network-on-chip, which not only causes increased power consumption of the network-on-chip, but also easily leads to flit transmission congestion, thereby affecting overall performance of a processor.